soc verification Jobs in Delhi

functional verification performance debugging rtl analysis uvm development test case design soc silicon validation formal verification axi fpga ahb system verilog pcie

soc design verification rtl design techniques static verification tools timing constraints development problem solving skills learning

rtl delivery test plan creation uvm methodology microcontroller architecture verilog / system verilog physical design soc axi ahb verification hardware eda verification engineer dft soc verification formal verification ddr pcie

digital design expertise protocol knowledge problem solving ability team leadership effective communication soc axi verification chip design asic design synopsys pcie

ip / soc verification advanced verilog knowledge debugging in simulation uvm / vmm / ovm test environments protocols expertise design verification system verilog chip design verification engineer synopsys pcie

soc design expertise verification methodologies rtl signoff techniques timing constraints development synthesis tools proficiency learning

rtl design techniques lint and cdc synthesis methodologies constraints development team leadership soc verification chip design verilog synopsys

digital verification scripting proficiency design debugging functional coverage ip integration soc digital design vmm system verilog chip design ovm uvm hdl synopsys

soc integration design verification cad software engineering scripting languages technical leadership algorithms c perl tcl san python team player problem solving design management

ip verification expertise eda tool proficiency uvm / vmm methodologies verilog / system verilog fault injection techniques soc verification design verification rtl design chip design ovm verification engineer synopsys eda tools

soc development expertise chip design execution functional leadership automotive processors knowledge cross functional coordination amp product development manufacturing action innovation npi implementation problem solving cutting

uvm testbench architecture system verilog expertise coverage closure techniques simulation debugging skills test plan creation soc design verification axi ahb synopsys pcie

soc uvm verilog synopsys pcie system verilog verification

dsp c assembly language programming tcl simulation models san python c

soc design execution chip development stakeholder engagement product lifecycle management technical leadership amp product development manufacturing action innovation npi implementation problem solving cutting

formal verification functional verification digital design hdl implementation scripting automation soc vmm system verilog chip design ovm uvm verification engineer synopsys

soc verification test plan creation uvm methodology verilog / system verilog debugging designs physical design axi ahb hardware eda verification engineer dft formal verification ddr pcie

functional verification performance verification debugging failures test bench development system verilog assertions soc silicon validation formal verification axi fpga ahb uvm pcie

digital design functional verification system verilog hdl implementation debugging techniques soc vmm chip design ovm uvm verification engineer synopsys

functional verification performance debugging uvm test development rtl analysis formal verification soc silicon validation axi fpga ahb system verilog pcie

soc design leadership chip development expertise automotive processors knowledge cross functional coordination technical standards engagement amp product development manufacturing action innovation npi implementation problem solving cutting

soc architecture design cross functional collaboration product development lifecycle advanced technology understanding team leadership experience conference program management problem solving infrastructure high performance computing

vlsi design sram architectures circuit implementation scripting automation digital fundamentals soc digital design verification chip design cmos schematic synopsys circuit design

vlsi design sram architectures circuit implementation scripting languages digital analog fundamentals soc digital design verification chip design cmos schematic synopsys circuit design

testability techniques eda tool expertise scripting automation post silicon debug rtl verification physical design soc atpg rtl design hardware gls dft eda tools

asic development flow digital design methodologies verilog and system verilog fpga prototyping flows scripting in python soc design compiler verification chip design dft synopsys

complex ip development architectural design high speed protocols hdl proficiency communication skills soc atpg silicon validation axi fpga ahb verification hardware verilog dft pcie

standard cell layout eda tools proficiency physical verification problem solving skills team collaboration soc cadence virtuoso drc chip design lvs digital circuits layout design synopsys

rtl design engineer automotive socs expertise verilog / system verilog coding functional safety knowledge tcl perl python proficiency digital design rtl coding verification ddr pcie synopsys

complex ip design dsp processor design high speed protocols hardware description languages testbench development soc atpg silicon validation axi fpga ahb verification verilog dft pcie

dft testing techniques eda tool proficiency scripting automation skills rtl verification expertise post silicon debugging physical design soc atpg rtl design hardware gls eda tools

circuit design expertise high speed protocols hdl proficiency complex ip development microcontroller architecture soc atpg silicon validation axi fpga ahb verification hardware verilog dft pcie

rtl design timing constraints static verification synthesis tools design verification learning

c / c programming soc architecture problem solving virtual prototypes embedded systems linux simulation models os mobile team player

c / c programming soc architectures serial bus protocols problem solving skills team collaboration linux simulation models os mobile team player

soc architecture design chip development management cross functional collaboration automotive technology expertise end to end product development conference program management problem solving infrastructure high performance computing

rtl design expertise static verification techniques timing constraints development team leadership skills debugging and diagnosis learning communication skills

physical verification power analysis chip level floorplanning scripting languages debugging techniques python infrastructure high performance computing perl tcl

physical verification automation power analysis techniques ir drop debugging chip level floorplanning scripting proficiency python infrastructure high performance computing perl tcl

physical design leadership timing closure expertise eda tools proficiency static timing analysis team collaboration skills rtl design verification hardware vlsi design signal integrity dft

rtl development timing constraints low power checks microcontroller architecture post silicon debug physical design rtl design axi ahb verification hardware hardware engineering dft ddr pcie

c / c proficiency problem solving skills project management team leadership hardware understanding software requirements debugging simulation models os team player

post silicon validation automated validation scripts c programming language microcontroller architecture embedded firmware development microprocessor usb rtos linux python

physical design timing closure tool proficiency scripting knowledge design optimization perl tcl python implementation engineer infrastructure high performance computing